1. Field of the Invention
The present invention relates to a semiconductor device including electrically rewritable semiconductor memory cells and a method of manufacture thereof.
2. Description of the Related Art
A nonvolatile semiconductor memory is one of the semiconductor memory devices. In recent years, the nonvolatile semiconductor devices are in increasing demand as data storage devices. As the typical electrically rewritable nonvolatile memories using floating-gate (FG) electrodes, NOR-type flash memory and NAND-type flash memory are known.
In order to increase the storage capacity of these flash memories, the dimensions of devices have been scaled down. However, shrinking the dimensions of devices have caused various problems, such as the increased aspect ratio of device structure, the effect on interference between adjacent FG electrodes, and the effect of variations in process on the injection of electrons into FG electrodes.
Since the NAND-type flash memory is advantageous to shrinking of the dimensions of devices, their storage capacity has been progressively increased. However, increasing the storage capacity has made problems of the short-channel effect (SCE) of transistors, the interaction (Yupin effect) due to coupling capacitance between adjacent FG electrodes, the reduced cell current by the miniaturization, and the difficulty in ensuring a sufficient coupling ratio between the control gate (CG) electrode-to-FG electrode capacitance (C2) and the FG electrode-to-substrate capacitance (C1). The coupling ratio is represented by C2/(C1+C2). Therefore, attempts are being made to contrive new memory cell structures.
In one of the conventional NAND-type flash memory cell structures, the coupling capacitance (C2) between FG and CG electrodes is made to increase by exposing the side of the FG electrode.
However, as the dimensions of devices shrink, the FG electrode becomes narrower in width and smaller in top surface area. As the result, it becomes difficult to ensure a sufficient coupling ratio.
There are variations in the process for exposing the side of the FG electrode. This produces variations in the width of the active area (AA). The variations in the AA width cause the coupling capacitance C1 between the FG electrode and the silicon substrate and the coupling capacitance C2 between the FG electrode and the CG electrode to vary. The variations of the coupling capacitances C1 and C2 result in a reduction in the yield of products.
With the conventional memory cell structure, in order to increase the cell current, it is required to increase the height of and the area of the side of the FG electrode. Increasing the height of the FG electrode leads to an increasing of the aspect ratio in the FG process. In terms of process, therefore, it is difficult to realize a high FG electrode. With the above method, therefore, it is difficult to increase the cell current.
In order to reduce the variations in the coupling capacitances C1 and C2 and to increase the cell current, a device structure has been proposed in which an FG electrode is formed on the side surface of a trench formed in the surface of a silicon substrate with a tunnel insulating film interposed therebetween (Jpn. Pat. Appln. KOKAI Publication No. 5-291586). With this device structure, however, limitations are encountered in increasing the coupling ratio. Moreover, since there are corners in the channel region, the writing (injecting electrons into the FG electrode) characteristics vary greatly according to their shape. Furthermore, in processing the CG and FG electrodes on the sidewall of the trench in the surface of the silicon substrate, there arises a problem in that the surface of the silicon substrate suffers etching.
As described above, the conventional flash memories have a problem that, with shrinking of device dimensions, it becomes more difficult to achieve a sufficient coupling ratio.